(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to methods used to fabricate metal oxide semiconductor field effect, (MOSFET), devices, with improved performance, and increased device density, via use of MOSFET process innovations.
(2) Description of Prior Art
Major objectives of the semiconductor industry continues to be increased device performance, and decreased process costs. The trend to micro-miniaturization, or the use of sub-micron features, have allowed these objectives to be successfully addressed. The creation of MOSFET devices, with sub-micron features, results in a reduction in performance degrading parasitic capacitances, while the use of sub-micron features allow the attainment of smaller semiconductor chips, however still accommodating the level of integration supplied by larger counterparts, thus enabling a greater number of smaller semiconductor chips to be obtained from a specific size starting wafer, thus reducing the processing cost for a specific semiconductor chip.
In addition to micro-miniaturization, basically obtained via advances in the photolithographic discipline in terms of more advanced exposure cameras, and more sensitive photoresist materials, specific MOSFET process sequences have also allowed specific MOSFET features to be reduced in size, and by so doing improve device performance. This invention will describe novel MOSFET process sequences used minimize specific MOSFET features, thus enhancing device performance. The formation of a source/drain extension, or a lightly doped source/drain, (LDD), region, accomplished after formation of other features, such as heavily doped source/drain regions, or polycide gate structures, allow this LDD region to maintain the minimum designed dimensions, as a result of avoiding the high temperature processes used for formation of heavily doped source/drain regions, or polycide gate structures. In addition these novel process sequences, used to create the source/drain extension, also allows the attainment of shallower, heavily doped source/drain regions, resulting from the diffusion from an overlying doped epitaxial layer, as well as resulting in a planar top surface topography, both contributing to increased device performance, and increased device density, or process cost reduction. Prior art, such as Hong, in U.S. Pat. No. 5,899,719, describes a sub-Micron MOSFET device, featuring a source/drain extension. However that prior art does not feature the use of selectively grown epitaxial silicon to define a subsequent gate region, and to supply the dopants needed for the heavily doped source/drain region.
It is an object of this invention to fabricate a MOSFET device, featuring source/drain extension regions, or an LDD regions, formed after formation of heavily doped source/drain regions, and after formation of polycide gate structures.
It is another object of this invention to form shallow, heavily doped source/drain regions, via diffusion from an overlying selective epitaxial grown, (SEG), silicon layer, prior to formation of the source/drain extension regions.
It is still another object of this invention to form a metal silicide layer on the gate structure, as well as on the top surface of the SEG silicon regions, prior to the formation of the source/drain extension regions.
It is still yet another object of this invention to provide a smooth top surface topography for the MOSFET device, by forming the gate structure between SEG silicon regions.
In accordance with the present invention a process for forming a MOSFET device, featuring source/drain extension regions, formed prior to high temperature procedures used to form heavily doped source/drain regions, as well as polycide gate structures, is described. A first iteration of this invention incorporates the formation of doped, SEG silicon regions, on a semiconductor substrate, with a channel region, located in the area of the semiconductor substrate, located between the doped, SEG silicon regions. After formation of first insulator spacers, on the sides of the doped SEG silicon regions, a gate insulator layer, and a polysilicon gate structure, are formed in the space between the first insulator spacers, located on the sides of the doped SEG silicon regions, with the polysilicon gate structure formed to the same height as the doped SEG silicon regions. Selective removal of the first insulator spacers, followed by an ion implantation procedure, create the source/drain extension regions, in an area of the semiconductor substrate located between the overlying, doped SEG silicon regions, and the overlying, polysilicon gate structure. The source/drain extension regions link to the heavily doped source drain regions, located under the doped SEG silicon regions, formed via diffusion from the overlying, doped SEG silicon regions, during previous process steps. Second insulator spacers are then formed, located between the doped SEG silicon regions, and the polysilicon gate structure, with the second insulator spacers overlying the source/drain extension regions, resulting in a MOSFET device with a planar top surface topography.
A second iteration of this invention features the formation of a metal silicide layer, on the top surface of the polysilicon gate structure, and on the top surface of the doped, SEG silicon regions, prior to removal of the first insulator spacers. After removal of the first insulator spacers, the source/drain extension regions are again formed in an area of the semiconductor substrate, located between the overlying doped SEG silicon regions, and the overlying polycide gate structure. Formation of the second spacers is again used, overlying the source/drain extension regions, and to fill the space vacated by the removal of the first insulator spacers.
A third iteration of this invention comprises the formation of L shaped, insulator spacers, located overlying the source/drain extension regions. This is accomplished by forming first insulator spacers on the sides of the doped SEG silicon regions, followed by the formation of an dielectric shape, located between the doped, SEG silicon regions, lined with the first insulator spacers. Selective removal of the first insulator spacers allow the formation of the source/drain extension regions, in an area of the semiconductor substrate, located between the overlying, doped SEG silicon regions, and the overlying dielectric shape. Removal of the first insulator spacers, and of the dielectric shape, is followed by the formation of dual dielectric spacers, on the sides of the doped SEG silicon regions, overlying the source/drain extension regions. Selective removal of the top layer, of the dual dielectric spacers, result in L shaped spacers, on the sides of the doped SEG silicon regions. Gate insulator growth, and polysilicon gate formation, in the region between the doped SEG silicon regions, lined with the L shaped spacers, are then employed.